1. Technical Field
The present application generally relates to three-dimensional NAND Flash memory and, more specifically, to systems and methods of adjusting the threshold voltages of control transistors for better performance during operation of a memory array.
2. Related Art
NAND Flash memory is a nonvolatile memory that is used in a wide range of applications including mobile phones, digital cameras, and solid-state hard drives. The high storage density of NAND Flash memory, especially when compared to NOR Flash memory, has played a large role in its market penetration. This storage density is achieved in part through the use of strings of memory cells connected in series between a ground line and bit lines, which reduces the number of metal contacts required. These strings are commonly called “NAND strings” due to their resemblance to NAND gates. Each memory cell within a NAND string can be addressed by a word line that the memory cell shares with neighboring cells of other NAND strings. In the past, NAND Flash memory has been implemented as a two-dimensional (planar) array defined by word lines and bit lines that intersect perpendicularly, with the memory cells being formed at those intersections.
The NAND string topology has been further developed to achieve still greater storage density. Such efforts have lead to the development of three-dimensional (3D) NAND Flash memory, in which memory cells are stacked vertically on top of one another.
FIG. 1 shows a schematic diagram illustrating a 3D NAND Flash array, as well as various transistors used for control. This figure shows four pages 150, 151, 152, 153 (Page 0 to Page 3), which contain a total of eight NAND strings 110. Each NAND string 110 includes a plurality of memory cells, such as the memory cell 112. Each memory cell can be addressed using at least one of the bit lines 140, 141 (BL0 and BL1), at least one of the string select lines 130, 131, 132, 133 (SSL0 to SSL3), and at least one of the word lines 120, 121, 120n (WL0 to WLn). The bit lines 140, 141 may connect to the memory planes 190, 191, which are different depths of the array structure, such that the memory planes associated with different bit lines may be stacked on top of one another in a z-direction 184. In the embodiment shown in FIG. 1, the bit line 140 (BL0) accesses the plane 190 (Plane 0) and the bit line 141 (BL1) accesses the plane 191 (Plane 1), which is above the plane 190. Furthermore, the bit lines 140, 141 may each be provided at opposite sides of the array structure.
String select lines 130, 131, 132, 133 may be connected to string select transistors 135, which are formed in string select structures on opposite sides of the array structure. These string select transistors connect the array structure to on-chip sense circuitry (not shown) attached to each bit line 140, 141. Each page may be associated with a unique string select line. As shown in the figure, the page 150 (Page 0) is accessible by the string select line 130, the page 151 (Page 1) is accessible by the string select line 131, the page 152 (Page 2) is accessible by the string select line 132, and the page 153 (Page 3) is accessible by the string select line 133. This allows an SSL signal travelling on a given string select line to select a given page (e.g., a stack) of memory cells, effectively setting an “x” coordinate in an x-direction 180. It should be further noted that each page may comprise multiple NAND strings 110, and each NAND string 110 may have an associated string select transistor 135.
The string select transistors 135 connected to even pages 150, 152 may form a first string select structure on one side of the array, and the string select transistors 135 connected to odd pages 151, 153 may form a second string select structure on the opposite side of the array.
The word lines 120, 121, 120n may be connected to gates of the memory cells. Accordingly, a WL signal may address a given memory cell within a selected NAND string, thereby setting a “y” coordinate in a y-direction 182.
Accordingly, each cell within the 3D NAND Flash array may effectively be addressable through “x,” “y,” and “z” coordinates. More specifically, the cells are addressable through signals on the control lines, and they may be addressed for read, program, and erase operations thereby. For example, the memory cell 112 may be addressed by sending and/or receiving signals on the string select line 133, the word line 120n, and the bit line 140. Control signals on unselected lines may additionally be required to perform a given operation.
The ground select lines 160, 161 (GSL(even) and GSL(odd)) and common source lines 170, 171 (CSL) may provide additional controllability, as described below with respect to FIG. 2. Referring back to FIG. 1, in some embodiments, the common source lines 170 and 171 are connected together.
It should be noted that the orientations of the strings in adjacent pages alternate between bit-line-end-to-source-line-end and source-line-end-to-bit-line-end, which results in the positions of the string select structure (which connects the array to the bit lines) and the common source line physically alternating between even pages and odd pages. For example, on even pages 150, 152, the word line 120 (WL0) is the nearest word line to the common source line 170. However, on odd pages 151, 153, the same word line 120 is the farthest from the common source line 171. Related U.S. Pat. No. 8,503,213 provides further detail into this topology, as well as the reasoning behind it, and is incorporated herein by reference for these and all other purposes.
As indicated in FIG. 1, the number of word lines may vary based on design considerations. While FIG. 1 shows four pages and two bit lines, the number of pages and bit lines may also vary based on design considerations.
FIG. 2 shows a schematic diagram illustrating two strings in an even page of the array structure shown in FIG. 1. Certain reference numerals are reused to represent similar structures and will not be described again. The NAND string 202 extends in the y-direction 182 and is connected to the bit line 140 (BL0). The NAND string 204 also extends in the y-direction 182 and is offset from the NAND string 202 in the z-direction 184 (e.g., on top of the NAND string 202). Accordingly, the NAND string 204 is in a different plane and is connected to the bit line 141 (BL1), which is associated with that plane. The NAND string 202 comprises the memory cells 220, 222, and 224, and the NAND string 204 comprises the memory cells 221, 223, and 225. These memory cells store information such as digital values (e.g., bits), whereas the other transistors function to control the array structure. As indicated in FIG. 2, the length (e.g., the number of memory cells) in the NAND strings 202 and 204 can vary.
The word line 120 is connected to the gates of the memory cells 220 and 221, the word line 121 is connected to the gates of the memory cells 222 and 223, and the word line 120n is connected to the gates of memory cells 224 and 225. The gates may be floating gates or other charge trapping structures that have alterable threshold voltages (V1). The word lines 120, 121, and 120n may be used to apply the voltages necessary to perform read, program, and erase operations. Further, the NAND strings 202 and 204 may be selected by the string select transistors 230 and 231, respectively, whose gates both receive signals on the string select line 130. As described above, the string select transistors 230 and 231 can connect and disconnect the NAND strings 202 and 204, respectively, from the bit lines 140 and 141, respectively. The ground select transistor 262 can connect and disconnect the NAND string 202 from the common source line 170, based on the signal received on the even ground select line 160. Similarly, the ground select transistor 263 can connect and disconnect the NAND string 204 from the common source line 170 using the same signal.
The NAND strings 202 and 204 may further depend on the upper ground select transistor 260 and 261, respectively, whose gates both receive signals on the upper ground select line (UGSL) 161. During fabrication, the upper ground select transistors 260 and 261 may result as a side effect of creating ground select transistors on odd pages (e.g., in a split-gate 3D NAND Flash architecture). Accordingly, the upper ground select line 161 may also be referred to as the odd ground select line 161. The upper ground select transistors 260 and 261 do not necessarily provide additional granularity of control for the even NAND strings 202 and 204 beyond what is provided by the string select transistors 230 and 231. Much like the string select transistors 230 and 231, the upper ground select transistors 260 and 261 can connect and disconnect the NAND strings 202 and 204, respectively, from the bit lines 140 and 141, respectively. Accordingly, the upper ground select transistors 260 and 261 may be removed, but the fabrication process may be greatly simplified through their inclusion.
Though not shown in this figure, NAND strings on odd pages may have a similar layout, with a reversed orientation in the y-direction 182. As a result, the positions of the bit lines and the common source lines may be switched. Furthermore, the odd ground select line 161 may be connected to ground select transistors of the odd NAND strings, and the even ground select line 160 may be connected to upper ground select transistors of the odd NAND strings. Also, as the odd NAND strings are on different pages, different string select lines and transistors may be used. The same word lines 120, 121, 120n may be connected to both even and odd NAND strings, though their relative proximity to the corresponding string select structure may be reversed.
The following is a description of a read operation, which illustrates the usage and importance of the control transistors (e.g., string select transistors, ground select transistors, and upper ground select transistors). If the memory cell 220 is to be read, signals on the string select line 130 and the upper ground select line 161 should exceed the Vt of the string select transistor 230 and the Vt of the upper ground select transistor 260, respectively. This allows the bit line 140 to be connected to the NAND string 202, which includes the selected memory cell 220. Furthermore, a signal on the ground select line 160 should exceed the Vt of the ground select transistor 262, so that the NAND string 202 is connected to the common source line 170. A read voltage may be placed on the word line 120 (WL0) corresponding to the selected memory cell 220, and a pass voltage may be placed on the other word lines 121 to 120n (WL1 to WLn). The read voltage may be selected to cause the memory cell 220 to conduct only if its Vt is below a certain level (e.g., 0 V). Conversely, the pass voltage can be chosen to cause all unselected memory cells on the NAND string 202 (e.g., the memory cells 222 and 224) to conduct independent of their respective threshold voltages. Under these conditions, the state of the memory cell 220, such as whether its Vt is above or below 0 V, may be determined by sense circuitry (not shown) connected to the bit line 140 using charge integration or other methods known in the art. This state can translate into a digital value (e.g., a bit). In the case of multi-level cell (MLC) NAND Flash, which is used in some embodiments, each memory cell can hold more than one bit. This can result in greater storage density, but it requires more precision, both when programming Vt values into each memory cell and when measuring these programmed Vt values.
It should be noted that the bit line 140 may also be connected to other NAND strings. When a read operation is performed on another NAND string connected to the bit line 140, the string select transistor 230 may be switched off to prevent leakage onto the bit line 140 caused by the NAND string 202, as any such leakage would negatively affect the read operation. Therefore, the Vt of the string select transistor 230 should not be exceeded during read operations of other NAND strings connected to the bit line 140.
As discussed above, if the control transistors are not properly configured, a variety of problems can arise. In general, an excessively low Vt can lead to slower programming speed, poor programming inhibition, and high leakage from unselected lines. Conversely, an excessively high Vt can lead to read fails, as desired memory cells may not be fully selectable. In some scenarios, uncontrolled threshold voltages may even lead to unintentional leakage between a common source line and a bit line, leading to degradation of the voltages on either or both lines. The string select transistors, the ground select transistors, and the upper ground select transistors directly impact the performance of read, program, and erase operations. The Vt distributions of these transistors should therefore be well controlled.
As briefly mentioned above, various challenges affect the fabrication of 3D NAND Flash arrays. For example, placing multiple memory cells on top of one another often requires trenches and vias with high aspect ratios. If the memory cells utilize charge trapping technology such as silicon-oxide-nitride-oxide-silicon (SONOS), it can be difficult to remove the oxide-nitride-oxide (ONO) layers from the non-memory transistors (e.g., control transistors) due to these high aspect ratios. This makes the formation of traditional gate oxides difficult. Accordingly, the control transistors may be designed using the same technology as the memory cells, e.g., having ONO layers, to simplify the fabrication process. As a result, the control transistors may include charge trapping structures similar to those of the memory cells, though the relative dimensions may vary.
While modifying the control transistors can decrease process complexity, it can also introduce new challenges. For example, gate-oxide-based control transistors can be designed to have intrinsically narrow Vt distributions (e.g., minor variability over the entire array), but this can be much more difficult for ONO-based control transistors. It is therefore highly desirable to tighten the Vt distributions of the control transistors to improve reliability and performance, while also increasing the associated process window.